1. Field
Exemplary embodiments of the present invention relate to an integrated circuit, and more particularly, to a fuse circuit disposed in the integrated circuit.
2. Description of the Related Art
Diverse integrated circuit chips use fuses to store data used for the operation thereof, such as a setup data and a repair data. A general fuse recognizes a data based on whether the fuse is cut by a laser or not. Therefore, a fuse may be programmed in the stage of wafer, but after the wafer is mounted on a package, the fuse may not be programmed. Therefore, an e-fuse is used. The e-fuse stores a data by using a transistor and changing the resistance between a gate and a drain/source of the transistor.
FIG. 1 illustrates an e-fuse including a transistor, where the e-fuse operates as a resistor or a capacitor.
Referring to FIG. 1, the e-fuse includes a transistor T, and a power supply voltage is applied to a gate G while a ground voltage is applied to a drain/source D/S.
When a power supply voltage of such a level that the transistor T may endure is applied to the gate G, the e-fuse operates as a capacitor C. Therefore, no current flows between the gate G and the drain D or the source S. However, when a voltage of such a level that the transistor T may not endure is applied to the gate G, the gate oxide of the transistor T is destroyed to short the gate G and the drain source D/S from each other. As a result, the e-fuse operates as a resistor R. Therefore, current flows between the gate G and the drain/source D/S.
Based on the above described features, the data of the e-fuse is recognized based on the resistance value between the gate G and the drain/source D/S of the e-fuse. The data of the e-fuse may be stably recognized by (1) forming the transistor T in a big size, or (2) using an amplifier, instead of increasing the size of the transistor T, and amplifying the current flowing through the transistor T. When the transistor T is formed in a big size, the data of the e-fuse may be recognized without performing an amplification operation. The above two methods, however, have limitation of dimensions because the transistor T that constitutes the e-fuse is to be designed big or each e-fuse is to be equipped with an amplifier for amplifying a data.
U.S. Pat. No. 7,269,047 discloses a technology of forming an e-fuse in a type of an e-fuse array in order to reduce the area occupied by the e-fuse. FIG. 2 is a block view illustrating a conventional e-fuse array circuit.
Referring to FIG. 2, the e-fuse array circuit includes a cell array having a plurality of memory cells 201, 202, 203 and 204, a row control circuit 210, a voltage providing circuit 220, and a column control circuit 230.
The memory cells 201, 202, 203 and 204 include memories M1, M2, M3 and M4 and switches S1, S2, S3 and S4, respectively. The memories M1, M2, M3 and M4 are e-fuses having the characteristics of resistors or capacitors depending on whether they are ruptured or not. In other words, the e-fuses M1, M2, M3 and M4 may be regarded as resistive memories for storing data based on the intensity of resistance. The switches S1, S2, S3 and S4 electrically connect the memories M1, M2, M3 and M4 with column lines BL0 and BL1 under the control of row lines WLR0 and WLR1.
The row control circuit 210 includes a row decoder 211 and a plurality of voltage transformers 212 and 213. The row decoder 211 activates a signal of a line selected between the row lines WLR0 and WLR1 to a logic high level and turns on a corresponding switch by decoding an address ADD. The voltage transformers 212 and 213 drive the voltage of program/read lines WLP0 and WLP1 to a logic low level when the signals of the row lines WLR0 and WLR1 inputted thereto are deactivated. When the signals of the row lines WLR0 and WLR1 inputted thereto are activated, the voltage transformers 212 and 213 provide the program/read lines WLP0 and WLP1 with a voltage P/R BIAS which is received from the voltage providing circuit 220.
The voltage providing circuit 220 supplies such a high voltage as to destroy the gate oxides of the e-fuses M1, M2, M3 and M4 (which is a voltage generated by pumping a power supply voltage) to the voltage transformers 212 and 213 when a program operation is performed (when the corresponding fuses are to be ruptured). When a read operation is performed, the voltage providing circuit 220 supplies a voltage of an appropriate level for performing the read operation, which is generally a power supply voltage, to the voltage transformers 212 and 213.
The column control circuit 230 includes a column decoder 231, a current limiter 232, and a sense amplifier 233. The column decoder 231 electrically connects a line selected between the column lines BL0 and BL1 with the current limiter 232 by decoding the address ADD. The current limiter 232 includes a transistor that is controlled based on a bias voltage and it sinks the current of the selected line between the column lines BL0 and BL1 to a ground voltage terminal. The sense amplifier 233 compares the voltage of a node between the current limiter 232 and the column lines BL0 and BL1 with a reference voltage VREF and senses a data. When a memory cell selected by the row decoder 211 and the column decoder 231 is ruptured, current flows through the current limiter 232. Therefore, the sense amplifier 233 generates an output data FUSE_DATA of a logic high level. When the selected memory cell is not ruptured, no current flows through the current limiter 232. Therefore, the sense amplifier 233 generates an output data FUSE_DATA of a logic low level.
Although FIG. 2 illustrates an e-fuse array circuit including four e-fuses, the e-fuse array circuit may include a plurality of e-fuses to have a capacity of several kilobits (kb) to tens of megabits (Mb).
FIG. 3 is a block view exemplarily illustrating an e-fuse array circuit in an integrated circuit chip. Referring to FIG. 3, the integrated circuit chip includes a plurality of internal circuits 311 to 313 and an e-fuse array circuit 320.
The e-fuse array circuit 320 stores various data to be used by the first to third internal circuits 311 to 313. The data stored in the e-fuse array circuit 320 are transferred to the first to third internal circuits 311 to 313 during the initial operation of the integrated circuit chip.
The first to third internal circuits 311 to 313 use a data FUSE_DATA transferred from the e-fuse array circuit 320. For example, the first internal circuit 311 may be a circuit for generating a plurality of internal voltages having a level decided based on the data FUSE_DATA transferred from the e-fuse array circuit 320. The second internal circuit 312 may be a circuit for performing diverse setup operations of the integrated circuit chip based on the data FUSE_DATA transferred from the e-fuse array circuit 320. The third internal circuit 313 may be a circuit for performing a repair operation for substituting a defective portion with a portion having no defect in the integrated circuit chip based on the data FUSE_DATA transferred from the e-fuse array circuit 320.
The first to third internal circuits 311 to 313 receives an optimum setup data for an operation and a trimming data from the e-fuse array circuit, and they may operate with optimum setup values. However, since the e-fuse array circuit 320 may not operate after obtaining the optimum setup value for itself, it may be difficult to make sure of stable operation of the e-fuse array circuit 320.